发明名称 LOGIC SIMULATION SYSTEM AND INPUT/OUTPUT CONTROLLER
摘要 <p>PROBLEM TO BE SOLVED: To enable a user to efficiently perform logic simulation and analysis without paying any attention to a troublesome procedure and operation regarding the logic simulation. SOLUTION: This system is equipped with a means which manages logic circuit data information made to correspond to signal terminals of a logic circuit, a means for displaying on a screen logic simulation result information in free-format display form displaying signal values of the signal terminals only at specified time and logic simulation result information in stream display format as the time-series display format of the signal values of the signal terminals including the specified time, and a signal value setting means which sets the changed signal values to the signal terminals for the logic circuit data information.</p>
申请公布号 JP2002132848(A) 申请公布日期 2002.05.10
申请号 JP20010264623 申请日期 2001.08.31
申请人 FUJITSU LTD 发明人 SATO AKIKO
分类号 G06F17/50;G06F19/00;(IPC1-7):G06F17/50 主分类号 G06F17/50
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