| 摘要 |
PROBLEM TO BE SOLVED: To provide a level conversion and semiconductor integrated circuit which avoids the problems of troublesome design of timing and of hampering system speeding up, which are caused because the signal receiving side circuit must fetches matching signal in timing with late signal as the change from low to high level of output signal is delayed, in comparison with that of high to low level. SOLUTION: A level conversion circuit is composed of a level shift circuit 12, which outputs in-phase and opposite phase signal with respect to the input signal and a post circuit which responds to an early signal from among output signals of the level shift circuit and generates output signal. An inverter circuit, each of which has two P/N channel type MOS transistors (Qp5, Qp6) (Qn5, Qn6) are connected in series, between a first and second voltage edge is set at the post circuit utilizing one pair as a transistor for input and the lest one pair is feedbacked, based on an output signal of the level shift circuit which is composed of respond swiftly for the next change.
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