| 摘要 |
PROBLEM TO BE SOLVED: To reduce layout area of a memory cell array. SOLUTION: Main word lines MWL00, MWL01 are arranged at a first row. Main word lines MWL10, MWL11 are arranged at a second row. Sub word lines SWL01, SWL00 are arranged at the first row, and connected to the main word lines MWL01, MWL00. Sub word lines SWL11, SWL10 are arranged at the second row, and connected to the main word lines MWL11, MWL10. AND gates WD00, WD01 activates the main word lines MWL00, MWL01 responding to a row selecting signal R10 and block selecting signals BS1, BS0. AND gates WD10, WD11 activates the main word lines MWL10, MWL11 responding to a row selecting signal R11 and block selecting signals BS1, BS0. |
