| 摘要 |
PROBLEM TO BE SOLVED: To prevent the generation of a clock signal whose pulse width is narrower than a normal one at the time of setting and releasing a power down mode, and also to prevent the generation of a through-current in a clock buffer in the power down mode. SOLUTION: The clock signal control circuit, which has a synchronization circuit 12 for supplying the clock signal inputted from the outside to the internal circuit of an integrated circuit or synchronizing a control signal that controls the supply so as to be stopped with the clock signal and a 1st AND circuit 16 for supplying the clock signal to the internal circuit with the output signal of the synchronization circuit as a gate signal, is provided with an OR circuit 18 for performing an OR operation of the control signal and the output signal of the synchronization circuit and a 2nd AND circuit 20 for ANDs the clocks signal and the output signal of the OR circuit and outputting an AND output as a clock signal to be inputted to the 1st AND circuit. |
