发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To prevent unnecessary stress from being applied to a memory cell in a previously verify-passed chip in a program/program-verify cycle, and a erase/erase-verify cycle in a simultaneous test of plural chips of a non-volatile semiconductor memory. SOLUTION: In a program/program-verify cycle and a erase/erase-verify cycle, a non-volatile storage element over-writen preventing circuit masks a mode enable-mask internal signal line 111 by a pass signal outputted by a memory control circuit 103 through a verify-pass signal line 110. Therefore, even if an active signal is inputted from a mode enable-mask signal line 118, since the mode enable-mask internal signal line 111 is masked, the program mode/ erase mode inputted from a mode selecting signal line 114 cannot be made active, unncessary stress for a memory cell array 104 can be eliminated.</p>
申请公布号 JP2002133879(A) 申请公布日期 2002.05.10
申请号 JP20000331999 申请日期 2000.10.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TACHIKAWA NAOHISA
分类号 G11C16/02;G11C29/00;G11C29/12;(IPC1-7):G11C16/02 主分类号 G11C16/02
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