发明名称 BAND LIMIT CIRCUIT, COMMUNICATION DEVICE, COMMUNICATION NETWORK SYSTEM, AND BAND LIMITING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a band limit circuit and band limiting method, capable of limiting a band at a PHY layer level in a communication network system as well as a communication device and communication network system capable of limiting a band for every communication line, by solving the problem of a band being difficult to be limited for each communication line which is provided to a user, because it is not possible to determine whether a plurality of packets have been transmitted on the same communication line. SOLUTION: A cycle counter 3 counts the number of clocks CLKA generated by frequency-dividing a transmission clock CLK. A comparator circuit 7 outputs a clear signal B1, when the count value exceeds the holding value of a cycle register 5. A limit counter 4 counts the number of clock CLKB of AND of an effective frame signal A1 and the clock CLKA. An over limit detecting circuit 8 outputs a limit exceedance detecting signal B3, when the count value B2 exceeds the holding value of a limit register 6. An effective frame signal control circuit 9 controls, when the over limit detecting signal B3 is inputted, so that the effective frame signal A1 is invalidated and outputs an effective frame signal A3.
申请公布号 JP2002135287(A) 申请公布日期 2002.05.10
申请号 JP20000325891 申请日期 2000.10.25
申请人 FUJIKURA LTD 发明人 KATAYAMA HIDEO;YAMADA YASUTO
分类号 H04L7/00;H04L7/02;H04L12/28;H04L12/44;H04L12/46 主分类号 H04L7/00
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