| 摘要 |
<p>A parallel operation device capable of readily performing inner product operation of vectors and efficient matrix computation. The parallel operation device (100a) comprises registers (120a to 120d) where operation elements, the objects of operation, are recorded, FMACs (140a to 140d) for performing product-sum operation of the recorded operation elements, and selectors (130a, 130b) provided between the register (120a) and the FMAC (140a). The selectors (130a, 130b) input the operation elements recorded in the register (120a) into the FMAC (140a) during matrix operation; and selects one of the registers (120a to 120d) in order during inner product operation and supplies the operation elements recorded in the selected register to the FMAC (140a).</p> |
