发明名称 MEMORY ACCESS CONTROL APPARATUS AND PROGRAM CONVERSION METHOD
摘要 PROBLEM TO BE SOLVED: To effectively read out data from a memory device of low-speed. SOLUTION: A CPU 11 sends out an offset address and a variable address to a system bus SYSAD sequentially for requiring look-ahead of the data. In response to this, a memory 13 writes the variable address in the offset address. An input-output I/O device 12, when detecting the offset address, generates a look-ahead address by using the variable address to send out the look-ahead address to the memory device 2. The memory device 2 sends out the data corresponding to the look-ahead address to the I/O device 12, which holds the data. The CPU 11 sends out the address of the data to the system bus SYSAD. The I/O device 12 decides whether the address is matched with the look-ahead address, and if both addresses agree, provides the data which is looked ahead and held in the CPU 11.
申请公布号 JP2002132575(A) 申请公布日期 2002.05.10
申请号 JP20000318221 申请日期 2000.10.18
申请人 SHARP CORP 发明人 IWASAKI YOICHI
分类号 G06F12/02;G06F9/38;G06F9/45;(IPC1-7):G06F12/02 主分类号 G06F12/02
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