| 摘要 |
PROBLEM TO BE SOLVED: To provide an input selector circuit constituted in a semiconductor integrated circuit, capable of shortening delay time while minimizing the increment of a layout area even when there are many inputs, and capable of canceling a critical pass. SOLUTION: The input selector circuit is constituted of clocked inverters CI1, CI2, CI3, intermediate node wires NET1, NET11, inverters INV0, INV1, INV2, INV3, a p-channel MOS transistor P3, input terminals IN1, IN2, IN3, an output terminal OUT, and selection terminals SEL1, SEL2, SEL3.
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