| 摘要 |
PROBLEM TO BE SOLVED: To provide a shift register in which area required for wiring is small. SOLUTION: In the shift register having (m) stages (m: integer of >=1) of a stage F1 storing either one of two kinds of state, each stage F1 has clock input terminals Ka, Kb, Kc inputting clock signals ϕa, ϕb, ϕc of (n) phase (n: integer of >=2) as terminals, an input terminal IN inputting a signal Gi-1 sent from an input terminal of the shift register or an output terminal of the previous stage, an output terminal OUT outputting a signal Gi sent to an input terminal of the post stage or an output terminal of the shift register, and each stage F1 inputs an initial state level for initializing a state of each stage F1 from any terminal out of the clock input terminals Ka, Kb, Kc. |
