发明名称 Gap-type metallic interconnect and method of manufacture
摘要 A method of manufacturing a gap-type metallic interconnect. A stack layer is formed over a substrate, wherein the stack layer is formed by stacking dielectric material layers having two different etching rates. A dual damascene opening is formed in the stack layer. A dielectric layer having the same etching rate as one of the dielectric material layers in the stack layer is formed to cover the sidewalls and bottom of the dual damascene opening. A portion of the dielectric layer is removed by an etch back process to expose the substrate at the bottom of the dual damascene opening. A barrier layer is then formed to cover the dielectric layer and the bottom of the dual damascene opening. The dual damascene opening is then filled with a metallic layer for forming a dual damascene structure. Finally, a wet etching is performed to remove the dielectric layer as well as a portion of the stack layer, thereby forming a gap-type dielectric structure. A plasma enhanced chemical vapor deposition is performed to deposit a layer over the substrate for subsequent processing.
申请公布号 US2002055243(A1) 申请公布日期 2002.05.09
申请号 US20000736918 申请日期 2000.12.14
申请人 UNITED MICROELECTRONICS CORP. 发明人 LEE CHIU-TE
分类号 H01L21/768;(IPC1-7):H01L21/320 主分类号 H01L21/768
代理机构 代理人
主权项
地址