MECHANISM AND METHOD FOR PIPELINE CONTROL IN A PROCESSOR

摘要

A data processing system including a memory system and a plurality of peripheral components. A processor is coupled to the memory and peripheral components. A plurality of pipeline stages are implemented within the processor where each stage is configured to perform specific operations according to instructions then associated with that stage. A snapshot register is associated with at least some of the pipeline stages where the snapshot register configured to store data describing the state of execution of the instruction then associated with that stage.