发明名称 METHOD AND DEVICE FOR CONTROLLING CACHE MEMORY
摘要 In order to immediately respond to an access request from a processor with reduced power consumption, a requested information is read out from a cache memory 31 or information buffers 421 to 424 and supplied to the processor when comparators 343 to 3410 output hit signals. The cache memory control method performs a first processing to read the tag from the tag memories 321 and 322 and temporarily store it in the tag buffers 351 and 352 when there is no hit signal output therefrom, performs a second processing to read the information from the cache memory 31 and supply it to the processor when a hit signal is output from the comparators 343 to 342 and to read the information from the main memory on the basis of the address signal AD, temporarily store the information in the information buffers 421 to 424 and the cache memory 31 and temporarily store the address of the information temporarily stored in the information buffers 421 to 424 in the backup buffer 39 when there is no hit signal output from the comparators 343 to 342.
申请公布号 US2002056026(A1) 申请公布日期 2002.05.09
申请号 US19990409881 申请日期 1999.10.01
申请人 MATSUYAMA HIDEKI 发明人 MATSUYAMA HIDEKI
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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