发明名称 Semiconductor memory and its test method
摘要 A semiconductor memory includes a test memory cell block and a test memory cell selector. The test memory cell block includes a plurality of memory cells that store bit values opposite to each other in adjacent memory cells. The test memory cell selector varies the potential of precharged bit lines by asserting one of the word lines of the test memory cell block, and selects as a memory cell to be tested, a memory cell that is connected to a bit line between the bit lines that changes their potentials in the test memory cell block. It can solve a problem of a conventional semiconductor memory in that it is very difficult to test the function of a circuit installed for suppressing the interference between adjacent bit lines.
申请公布号 US2002054526(A1) 申请公布日期 2002.05.09
申请号 US20010879173 申请日期 2001.06.13
申请人 UTSUMI TAKASHI;ADACHI KIYOSHI 发明人 UTSUMI TAKASHI;ADACHI KIYOSHI
分类号 G01R31/28;G11C17/00;G11C29/02;G11C29/24;(IPC1-7):G11C7/00 主分类号 G01R31/28
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