发明名称 METHOD AND DEVICE FOR GENERATING DELAY TEST PATTERN
摘要 PROBLEM TO BE SOLVED: To make generable a delay test pattern without changing the structure of an ON pass even when a critical pass subjected to a delay test is a reconverged pass. SOLUTION: This method includes a step S1 of generating a delay test circuit model D1; a step S8 of tracking the ON pass to detect the reconverged pass, judging the presence of a predetermined reconverged pass in the reconverged pass, advancing to delay test pattern generation steps S2-S7 when it is absent, and advancing to step S9 when it is present; the step S9 of cutting the branch start point of the specified reconverged pass into the ON pass and an OFF pass in the presence of the specified reconverged pass in the step S8; and a non-control value set step S10 of setting a non-control value having no influence on a transition pattern inputted to the ON pass to the OFF pass separated in the step S9 and advancing again to the step S8.
申请公布号 JP2002131399(A) 申请公布日期 2002.05.09
申请号 JP20000327598 申请日期 2000.10.26
申请人 NEC MICROSYSTEMS LTD 发明人 FUDA TOMOTSUGU
分类号 G01R31/3183;G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/318 主分类号 G01R31/3183
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