| 摘要 |
PURPOSE: A down conversion processor of a digital TV is provided to save a memory of an SDTV video decoder capable of decoding SD and HD input formats and selectively perform 1/2 down conversion and 1/4 down conversion according to the down conversion modes. CONSTITUTION: A down conversion processor of a digital TV includes a variable length decoder(110) for analyzing a compressed bit stream, an inverse quantizer(120) for inverse-quantizing the compressed bit stream using a DCT coefficient analyzed through the variable length decoder, and an inverse discrete cosine transformer(140) for performing 8x8 inverse discrete cosine transform for each block of the bit stream output in a macro block form from the inverse quantizer. The down conversion processor further includes a motion compensator(160) for compensating for motion of up-sampled data using motion signals extracted from the variable length decoder, and a macro block adder(150) for adding up data extracted from a frame memory(180) to output a restored block. The processor also has a down converter(220) for adaptively down-sampling pixel data output from the adder and storing the data in the frame memory, and an up-converter for up-sampling the data output from the frame memory. |
