Microprocessor and address translation method for microprocessor

摘要

A microprocessor (10) is equipped with an address translation mechanism (18) for performing dynamic address translation from a virtual address to a physical address on a page-by-page basis. The microprocessor includes a large-capacity low-associativity address translation buffer (22), and is capable of avoiding limitations imposed on a TLB entry lock function, while reducing the overhead for address translation. The address translation mechanism comprises an address translation buffer having an entry lock function, and control logic (20) for controlling the operation of the address translation buffer (22). The address translation buffer includes a lower-level buffer (50) organized as a lower-level hierarchy of the address translation buffer (22) and having no entry lock function, and a higher-level buffer (30) organized as a higher-level hierarchy of the address translation buffer (22) and having an entry lock function, the higher-level buffer having higher associativity than the associativity of the lower-level buffer. <IMAGE>