发明名称 Device and method for selectively powering down integrated circuit blocks
摘要 <p>Presented is a power down circuit for use in a system on Chip SOC. Within the SOC are several circuit blocks, each of them having a local clock. A system clock is coupled to the circuit blocks and is structured to act as the local clock of selected circuit blocks. A power control manager provides a signal that at least partially determines whether the system clock will act as the local clock for some of the circuit blocks. Within the circuit blocks is a local power control structured to selectively maintain the system clock as the local clock of the block after the local power control receives a signal to shut down the block from the power control manager, if the block is currently busy when the signal to shut down the block is received. Also presented is a method that can be operated using the above system. The method includes generating a system clock signal that is for use as a local clock signal for circuit blocks that have not been shutdown. A shutdown request signal is generated to selectively power down some of the circuit blocks. That shutdown request signal is transmitted to a power down circuit within the circuit block to be shutdown. The power down circuit receives the signal to power down the circuit block, as well as a current status of the block. After an evaluation, the cirucuit block is shut down if the signal to power down is received and the circuit block is presently idle. <IMAGE></p>
申请公布号 EP1204017(A1) 申请公布日期 2002.05.08
申请号 EP20000830732 申请日期 2000.11.03
申请人 STMICROELECTRONICS S.R.L. 发明人 FRANCIS, RUSSELL;ALIA, MICHELE
分类号 G06F1/32;(IPC1-7):G06F1/32 主分类号 G06F1/32
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