Redundant scheme for CAMRAM memory array

摘要

A content addressable memory (CAM) structure and method that provides a redundant scheme for an ASIC. The scheme comprises a CAM comparative means for bypassing normal encoders, including a fuse structure having a fuse address list and a "CAM row compare" structure. Redundancy is provided in "CAM Search Read" and "CAM Search Read and RAM Read" operations. Normal CAM memory address rows and redundant replacement CAM memory address rows are provided for bank addresses. A miss logic is provided for detecting a bank address miss and generating a responsive miss signal, and an "address out" logic is also provided to pass only one of a generated normal CAM memory address row, redundant replacement address row or miss signal in a bank. The method and structure can support different address sizes and different cache sizes.