| 摘要 |
A variety of applications do not require a high data throughput. The standardization of the interface in the field of smart cards fixes the processing width at 1 bit. Therefore, it is effective to use a programmable structure which operates with a data width of one bit. A data processing arrangement in the form of a 1-chip implementation with a processing width of 1 bit can be used in chip cards for simple control and automation functions while utilizing serial protocols. This structure features uncomplicated circuitry, a small chip surface area, a wide field of application and a low power consumption. The programmable data processing arrangement includes an ALU (10), which is based on a 1-bit processing structure, and a data memory (50) which is realized as an end-around shift register (52) having a word width of 1 bit; data can be serially applied to the ALU (10) from data outputs by unidirectional shift operations and the ALU (10) can apply data serially, via a common data input, to the shift register (52) which can be partitioned; a partition thereof, once activated by selection, remains active until an instruction activates another partition, and data can be applied to the ALU (10) from the data output (SOa) at the end of the partition and data can be applied from the ALU to the data input (SIa) of the partition at the beginning of the partition.
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