| 摘要 |
A delay stage for use in a voltage-controlled delay chain of a delay locked loop or in a voltage-controlled ring oscillator of a phase locked loop has pullup and pulldown transistors driven by a first input to the delay stage, at least one of which is in series with a delay control transistor, and a second pullup and pulldown transistor gated by a second input to the delay stage. When used in a delay chain, the first input is driven by a signal that leads the second input to the delay stage.
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