| 摘要 |
A method of integrating salicide process and self-aligned contact process is performed on a semiconductor substrate on which a plurality of doped gate electrodes and source/drain regions are formed in both a memory device area and a peripheral area. An oxide layer is formed on the exposed surface, and then a plurality of spacers is formed on the sidewalls of the gate electrodes respectively. Sequentially, a barrier layer and a buffering layer are formed on the exposed surface. Next, the buffering layer and the barrier layer are removed from the top of the gate electrodes to expose the oxide layer. The exposed oxide layer and the underlying gate electrodes are then removed until the gate electrode reaches a predetermined height. The salicide process is performed to form a silicide on the exposed surface of the gate electrodes and simultaneously on the source/drain regions in the periphery area. Next, a gate cap layer is formed on the silicide overlying the gate electrodes. After forming an inter-layer dielectric on the exposed surface, the self-aligned contact process is performed to form a contact hole to expose the source/drain region positioned between adjacent gate electrodes in the memory device area.
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