| 摘要 |
A method used inside a static timing analyzer, or any timing-driven tool, to reduce the memory required to store the timing values. A static timing analyzer stores the arrival times and the required times at every pin of a digital circuit design. As circuit density increases, the number of pins increases proportionately. In order to be able to handle such large designs it is desirable to keep the memory requirement to a minimum, without compromising the performance. The technique presented herein produces significant memory requirement reduction for design with multiple clocks, or multi-cycle paths, with very little performance penalty. In a preferred embodiment of the invention, the method is carried out by the steps of:1) Setting and propagating source triggering edges forward;2) Determining target triggering;3) Propagating the target triggering edges backward;4) Determining the propagation bins; and5) Finding a timing values translation function.
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