发明名称 MOS semiconductor device with shallow trench isolation structure and manufacturing method thereof
摘要 A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or "offset" towards a shallower part. Appropriately adjusting the implantation condition permits a retrograde well, which inherently has its peak near the bottom of the buried oxide film, to become shallower only in the well boundary region to thereby enable elimination of unwanted inversion of a parasitic MOS transistor element.
申请公布号 US6384455(B1) 申请公布日期 2002.05.07
申请号 US19980163362 申请日期 1998.09.30
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NISHIGOHRI MASAHITO
分类号 H01L21/76;H01L21/265;H01L21/266;H01L21/762;H01L21/8238;H01L27/092;H01L29/10;(IPC1-7):H01L29/76 主分类号 H01L21/76
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