发明名称 SAMPLING CLOCK GENERATING CIRCUIT, DATA TRANSFER CONTROL DEVICE AND ELECTRONIC DEVICE
摘要 PURPOSE: A sampling clock generating circuit, a data transfer control device and an electronic device are provided to generate a high-frequency clock with a simple circuit configuration. CONSTITUTION: A clock generation circuit comprising first to Nth inversion circuits in which an output of each previous-stage Kth(1<K<N-1) inversion circuit is connected to an input of the corresponding next-stage(K+1)th inversion circuit and an output of the Nth inversion circuit is connected by a feedback line to an input of the first inversion circuit, and first to Nth buffer circuits having inputs connected to outputs of the first to Nth inversion circuits, wherein the first to Nth inversion circuits are disposed along a first line that is parallel to the feedback line, and wherein the first to Nth buffer circuits are disposed along a second line that is parallel to the feedback line but different from the first line.
申请公布号 KR20020033433(A) 申请公布日期 2002.05.06
申请号 KR20010064264 申请日期 2001.10.18
申请人 SEIKO EPSON CORPORATION 发明人 KAMIHARA YOSHIYUKI
分类号 G06F13/42;G06F1/06;H03K3/03;H03L7/099;H03L7/18;H04L7/02;H04L7/033;(IPC1-7):G06F13/00 主分类号 G06F13/42
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