DIGITAL PHASE LOCKED LOOP BY MEASUREMENT OF PHASE ERROR

摘要

PURPOSE: A digital phase locked loop by a measurement of a phase error is disclosed to provide a reference time of an artificial satellite by compensating for an error and a noise of an IPPS signal from a GPS receiver. CONSTITUTION: The digital phase locked loop synchronizes a GPS 1PPS signal with a UTC. A phase error detector(21) calculates an error between a GPS 1PPS signal and internal 1Hz of a processor according to a reference signal. A software filter(22) reduces jitter amount of a compensated 1PPS signal which is provided to a DPLL based on the error calculated by the phase error detector(21) using a digital filter method. An error compensator(23) compensates for the 1PPS signal by the error compensated by the software filter(22) and provided the compensated IPPS signal to an input terminal of a DPLL.