发明名称 |
Fail number detecting circuit of flash memory |
摘要 |
A semiconductor memory device includes a memory cell array, a plurality of latch circuits, first circuit, second circuit and third circuit. The memory cell array has electrically rewritable nonvolatile memory cells arranged therein. The plurality of latch circuits temporarily hold data read out from the memory cell array. The first circuit is configured to generate a first current varying in proportion to "1" or "0" of binary logical data of one end of the plurality of latch circuits. The second circuit is configured to generate a second preset current. The third circuit is configured to compare the first current with the second current. The number of "1" or "0" of binary logical data of one end of the plurality of latch circuits is detected based on the result of comparison between the first current and the second current.
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申请公布号 |
US2002051385(A1) |
申请公布日期 |
2002.05.02 |
申请号 |
US20010985017 |
申请日期 |
2001.11.01 |
申请人 |
HOSONO KOJI;IKEHASHI TAMIO;TANAKA TOMOHARU;IMAMIYA KENICHI;NAKAMURA HIROSHI;TAKEUCHI KEN |
发明人 |
HOSONO KOJI;IKEHASHI TAMIO;TANAKA TOMOHARU;IMAMIYA KENICHI;NAKAMURA HIROSHI;TAKEUCHI KEN |
分类号 |
G11C16/02;G11C16/04;G11C16/06;G11C16/34;G11C29/04;G11C29/12;(IPC1-7):G11C11/34 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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