发明名称 |
Memory device with pipelined address path |
摘要 |
In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array.
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申请公布号 |
US2002051388(A1) |
申请公布日期 |
2002.05.02 |
申请号 |
US20010920780 |
申请日期 |
2001.08.01 |
申请人 |
MARTIN CHRIS G.;MANNING TROY A. |
发明人 |
MARTIN CHRIS G.;MANNING TROY A. |
分类号 |
G11C7/10;G11C8/00;G11C8/06;(IPC1-7):G11C29/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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