SEMICONDUCTOR MEMORY DEVICE USING SYSTEM CLOCK AS WRITE DATA FOR TEST

摘要

PURPOSE: A semiconductor memory device using a system clock as a write data for a test is provided to generate the write data for test by using only a system clock without using a data input/output pin. CONSTITUTION: A system clock(SCLK) is applied to a clock delay portion(350) and one or more data reception portions(300,310). The system clock(SCLK) applied to the clock delay portion(350) is changed to a delay data signal by a delay circuit selection portion. The delay circuit selection portion is controlled by a plurality of delay circuit and a control signal(SCTRL). The data reception portions(300,310) are enabled or disabled by the system clock(SCLK). The data reception portions(300,310) receives a delay data signal(DCLK) and generates an internal data. The data reception portions(300,310) are formed with D-FlipFlops.