| 摘要 |
A semiconductor memory device comprising an architecture for minimizing the lengths of the I/O (input/output) data paths and the difference in length between the data paths. In one aspect, a semiconductor memory device comprises first and second pad groups, first, second, third and fourth banks and first and second circuits. The first pad group comprises a portion of the total number of pads and is located in proximity to the center of the chip, and the second pad group comprises the remaining pads. The first, second, third and fourth banks include first and second, third and fourth, fifth and sixth and seventh and eighth blocks having memory cells, respectively, and further include first and second, third and fourth, fifth and sixth and seventh and eighth I/O units for inputting and outputting the data in the first through fourth blocks, respectively. The first circuit is connected between the first pad group and the odd-numbered I/O units of the banks, and performs multiplexing. The second circuit is connected between the second pad group and the even-numbered I/O units of the banks, and performs multiplexing. The banks and circuits are disposed on the semiconductor device such that the data buses connecting the corresponding banks and circuits are substantially the same length and width. Each of the first and second circuits can be replaced with a plurality of I/O sense amplifiers, and the I/O units can be replaced with I/O multiplexers.
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