Computer system with two phase checkpoints

摘要

A computer system in which first and second phase checkpoint steps (B1 A6, A7) are applied in order to facilitate fault recovery. Cache flush hardware (4a-4b) is arranged to execute a cache flush operation independently of the processors (2a-2b), including cache flush starters (5a-5b) for starting the cache flush hardware, and cache flush end detectors (6a-6b) for detecting the end of the cache flush operation. During the first phase checkpoint step, the cache flush operation and normal data processing are executed in parallel, and most of the dirty data in the cache memory (3a-3b) are written back into the main memory (9). When the cache flush end detectors detect the termination of the cache flush operation, the processors suspend the normal data processing operation, and in the second checkpoint step, the processors save (A6) the context of the processors in the main memory and the cache flush hardware is invoked (A7) again so that all the dirty data in the cache memory is written back into the main memory.