Sub word line drive circuit for semiconductor memory device

摘要

A semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines correspond to each one of the main word lines. A plurality of sub word line drivers are also included, wherein each sub word line driver corresponds to one of the sub word lines and connects the corresponding sub word line to the corresponding main word line. The sub word line drivers charge the sub word lines up to a boosting voltage regardless of an activation order between a sub word line selection signal and the main word line. The sub word line drivers can include a first transistor for transferring the sub word line selection signal to the sub word line in response to an activation of the main word line. A second transistor is configured to connect the main word line to the sub word line in response to an activation of the sub word line selection signal. A third transistor is configured to connect the main word line to a gate of the first transistor in response to a high voltage. And a fourth transistor is configured to connect the sub word line selection signal to a gate of the second transistor in response to the high voltage.