发明名称 Apparatus and method for an encoder interface module
摘要 In a processing system having a central processing unit and a plurality of modules units for receiving signals from encoder/sensor units, an encoder interface module can count the pulses in an incoming signal train. The encoder interface module has a plurality of registers and a compare unit for the generation of flags when the number of counted pulses has a predetermined relationship with numeric values stored in the registers. The encoder interface unit has apparatus for exchanging signal groups with an inter-module network. The inter-module network permits signal groups to be exchanged between interface modules without intervention of the central processing unit. The exchanged signal groups can coordinate the activity of the encoder modules.
申请公布号 US2002050939(A1) 申请公布日期 2002.05.02
申请号 US20010904242 申请日期 2001.07.12
申请人 YU ZHENYU 发明人 YU ZHENYU
分类号 H03M1/30;(IPC1-7):H03M1/12 主分类号 H03M1/30
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