发明名称 Video decoder capable of controlling encoded video data rate
摘要 <p>An MPEG video decoder capable of preventing a buffer for storing a video stream from overflowing and/or underflowing. The video decoding apparatus decodes a coded video bit stream including a series of pictures to produce decoded pictures. The video decoding apparatus includes: a bit buffer(2) for temporarily storing the video bit stream, a decoding circuit(4) for receiving the video bit stream output from the bit buffer(2) and decoding the video bit stream to produce decoded pictures, and a video bit stream control circuit(3,5,6,7) for controlling an amount of the video bit stream to be supplied to the decoding circuit(4) from the bit buffer(2) based on an amount of data of the video bit stream stored in the bit buffer(2). &lt;IMAGE&gt;</p>
申请公布号 EP0713341(B1) 申请公布日期 2002.05.02
申请号 EP19950118011 申请日期 1995.11.15
申请人 SANYO ELECTRIC CO. LTD 发明人 OKADA, SHIGEYUKI;KAWAHARA, KEITA;TANAHASHI, NAOKI;NAKASHIMA, HAYATO
分类号 G06T9/00;H04N7/32;H04N7/46;H04N7/50;(IPC1-7):H04N7/50;H04N7/26 主分类号 G06T9/00
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