PURPOSE: A CP flip flop is provided to perform high speed operation in a circuit with lower power at the small area compared with the existing flip-flop. CONSTITUTION: A clock delay section(210) inverts and delays a clock signal in response to an enable signal. A switch section(220) includes a plurality of switches and switches input data in response to and the clock signal and an output signal of the clock delay section(210). The switch section(220) includes a first switch(221) for switching the input data in response to the clock signal and a second switch(222) for switching an output signal of the first switch(221) in response to the output signal of the clock delay(210). A latch(230) stores at least one output signal of the switch section(220). The latch(230) includes a fourth inverter(231) and a fifth inverter(232). An input terminal of the fourth inverter is connected to the second switch(222). An input terminal of the fifth inverter(232) is connected to an output terminal of the fourth inverter and an output terminal of the fifth inverter(232) is connected to an input terminal of the fourth inverter.
