发明名称 |
Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses |
摘要 |
A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer. In reading data from the FIFO buffer, the read pointer address register is loaded with the previously saved write-pointer address associated with the beginning of each data block that is subsequently read. Since both the beginning and ending write-pointer addresses associated with each data block are captured and saved, the system reading from the FIFO buffer delineates between adjacent data blocks, thereby eliminating data overlap or FIFO interruption.
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申请公布号 |
US6381659(B2) |
申请公布日期 |
2002.04.30 |
申请号 |
US19990232764 |
申请日期 |
1999.01.19 |
申请人 |
MAXTOR CORPORATION |
发明人 |
PROCH TIMOTHY;HORGAN NICK |
分类号 |
G06F3/06;G06F5/06;G06F5/10;G06F5/12;G06F5/14;(IPC1-7):G06F12/02;G06F13/12;H04J3/02;G11C7/00 |
主分类号 |
G06F3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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