| 摘要 |
Even if duty is shifted to either a state in which an "H" period is long or a state in which an "L" period is long, the duty is recovered to about 50%.A duty correction circuit corrects a duty shift or deviation developed when analog complementary cycle signals having a phase difference of about half cycle therebetween and a duty ratio of about 50% are converted to logic levels, through the use of, for example, serial two-stage NAND gate static latches. The NAND gate static latches perform a latch operation when "H" periods of complementary clock signals are long, thereby to carry out a duty-of-about 50% correction, and perform an invert operation when "L" periods of the complementary clock signals are long, thereby recovering duty to about 50% even with respect to either the state in which the "H" period is long or the state in which the "L" period is long, according to only the levels of the input complementary clock signals and logic operations from timings without outputting narrow or thin pulses equivalent to derivative waveforms due to internal small delays.
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