发明名称 |
Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
摘要 |
A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.
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申请公布号 |
US6381167(B2) |
申请公布日期 |
2002.04.30 |
申请号 |
US20010781238 |
申请日期 |
2001.02.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA;MITSUBISHI ELECTRIC ENGINEERING COMPANY LIMITED |
发明人 |
OOISHI TSUKASA;TANIZAKI HIROAKI |
分类号 |
G11C11/401;G11C7/18;G11C11/409;G11C29/00;H01L21/3205;H01L21/8242;H01L27/108;(IPC1-7):G11C5/06 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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