| 摘要 |
A signal processing circuit capable of deciding and storing the starting packet and realizing normal data storage when packet loss occurs at the time of reception of divided packets of a serial interface and a method of the same. Processing for storage of a normal packet to an FIFO is carried out by deciding the starting packet and deciding there is packet loss when packet loss occurs and a packet does not arrive in the middle by using the value of a data block continuity counter, the value of the fraction number, and the value of the data base size set in the first quadlet of a CIP header 1 of the divided packet transmitted in for example a divided manner through an IEEE 1394 serial bus via a link core.
|
