发明名称 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
摘要 A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.
申请公布号 US6380084(B1) 申请公布日期 2002.04.30
申请号 US20000678621 申请日期 2000.10.02
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING INC. 发明人 LIM YEOW KHENG;SEE ALEX;CHA CHER LIANG;GUPTA SUBHASH;GOH WANG LING;TSE MAN SIU
分类号 H01L21/3205;H01L21/768;H01L23/532;(IPC1-7):H01L21/44 主分类号 H01L21/3205
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