发明名称 PARITY CHECK VERIFYING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To enable sure and simple verification of a parity check circuit by adding a simple circuit. SOLUTION: The parity check circuit checks serial data outputs 7 and 8 with parity bits of a serial-parallel converter 1 of a first parity check circuit A and a serial-parallel converter 1' of a second parity check circuit B with each other to output parity error detection signals 6 and 6' from second parity bit generators 2B and 2B'. The parity check circuit comprises means 9 and 9' like short circuit plugs for forcibly inputting erroneous signals to the first and second parity bet generators 2A and 2B of the first parity check circuit A, thereby verifying whether the parity check function is normally operated or not.
申请公布号 JP2002124934(A) 申请公布日期 2002.04.26
申请号 JP20000312526 申请日期 2000.10.12
申请人 YASKAWA ELECTRIC CORP 发明人 MASUZAKI KATSUHIKO;MITSUDA KENJI
分类号 G06F11/08;G06F12/16;G06F13/00;H04L1/00;H04L1/24;(IPC1-7):H04L1/00 主分类号 G06F11/08
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