PLL CIRCUIT AND FREQUENCY-DIVIDING METHOD

摘要

PURPOSE: A PLL(Phase Locked Loop) circuit and a frequency-dividing method are provided to reduce spurious noise level containing in a generating output by using a simple configuration. CONSTITUTION: The PLL circuit performs fractional dividing containing a phase comparator(20) outputting a phase difference signal, in correspondence with phase difference by comparing phases of two signals, a charge pump(21) generating in correspondence with phase difference signals(ΦSP,ΦSR), and a low-pass filter(11) and a voltage control generator(12). The PLL circuit further includes a control circuit(23), a delay circuit(22) and a selection circuit(24) for modulating the phase difference signal supplied to the charge pump(21).