发明名称 BUS SYSTEM
摘要 PROBLEM TO BE SOLVED: To make the intervals between memory modules narrow since a certain interval is necessary as the efficiency of transmission, i.e., the degree of coupling, and should not be less than the wiring length that a directional coupler occupies although bus-connected module intervals are determined by the wiring length. SOLUTION: Since a wire (main line) from a memory controller is made to have open ends or short-circuit ends and signals can be generated in both the directions of the directional coupler by using a progressive wave and a reflected wave, DRAMs can be connected to both the sides of the coupler. Consequently, the wiring length of the coupler is reducible to a half of the pitch between modules, so that high-density mounting becomes possible.
申请公布号 JP2002123345(A) 申请公布日期 2002.04.26
申请号 JP20010202914 申请日期 2001.07.04
申请人 HITACHI LTD 发明人 OSAKA HIDEKI;HATANO SUSUMU;KOMATSU TOYOHIKO;HARA ATSUSHI
分类号 G06F3/00;G06F12/00;G06F13/16;(IPC1-7):G06F3/00 主分类号 G06F3/00
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