Device for coding a sub-assembly for detection and correction of memory errors in a microprocessor and memory circuit, where the coding device is placed in series, acting in pipeline mode, with the processor prior to the memory

摘要

Coding device for a sub-assembly for detection and correction of memory errors in an electronic system comprising a microprocessor (10) and a memory (11). The device comprises a coding element (20) placed in series with the memory and structured in a pipeline stages so that it has the same data transfer rate as the processor when it writes to memory, particularly during block data transfer. An Independent claim is made for a coding method for a sub-assembly for detection and correction of memory errors in an electronic system.