| 摘要 |
<p>A defect redress analysis treating method capable of reducing a time required for the defect redress analysis treatment of a memory formed in a multi-bit redundancy and a memory testing apparatus having the defect redress analysis treating device performing the method; the method, comprising the steps of installing a plurality of redress analyzing units in a common defect analysis memory, simultaneously operating the plurality of redress analyzing units parallel with each other, and performing the redress analyzing treatment of the defective memory cell of a plurality of data bits read from the defective analysis memory in the plurality of redress analyzing units simultaneously parallel with each other so as to shorten the time required for the defect redress analysis treatment.</p> |
