| 摘要 |
An internal clock signal generating circuit includes a phase comparing circuit which is made active in accordance with a control signal SEN which becomes intermittently active in a power down mode from an operation permission signal generating circuit, receives an external clock signal and an output from a delay circuit, and compares phases of the signal and the output with each other, an address generating circuit for receiving a phase comparison result and generating a delay amount control signal for controlling a delay amount, and an address decoder for receiving an output of the delay circuit and generating a decode signal for controlling the delay amount.
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