| 摘要 |
A circuit 2 for generating a modified clock signal from an input clock signal is provided by a delay line formed of digitally controlled delay line elements between DE1, DE2, DE3, DE4 which a state change propagates. The feedback control applied to the delay line may be arranged such that the system is only stable when locked upon a state in which a predetermined number of signal changes are propagating along the delay line. The digital control of the delay line elements may be Gray coded.
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