| 摘要 |
<p>A method for hierarchical specification and modeling of scheduling in systemlevel simulations. A static scheduler is synthesized by a Virtual Component Codesign (VCC) process and comprises a simple sequential execution of the run functions (1-3) of behavious A-F. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. Two orthogal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol. The protocol itself is implemented by a pair of abstract interfaces, which in turn are implemented in concrete schedulable and scheduler objects in the simulator.</p> |
