| 摘要 |
Semiconductor processing methods of forming integrated circuitry, and in particular, methods of forming such circuitry utilizing dual damascene technology, and resultant integrated circuitry constructions are described. In one embodiment, a substrate is provided having a circuit device. At least three layers are formed over the substrate and through which electrical connection is to be made with the circuit device. The three layers comprise first and second layers having an etch stop layer interposed therebetween. A contact opening is formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed relative to the etch stop layer and defines a trough joined with the contact opening. Conductive material is subsequently formed within the trough and contact opening. In another embodiment, a contact opening is formed through a plurality of layers and has an aspect ratio of no less than about 10:1. A trench is defined in an uppermost layer of the plurality of layers proximate the contact opening. Conductive material is formed within the contact opening and at least a portion of the trench, with the conductive material being in electrical communication.
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