发明名称 PROCESSOR PERFORMING PARALLEL OPERATIONS SUBJECT TO OPERAND REGISTER INTERFERENCE USING OPERAND HISTORY STORAGE
摘要 When a register interference state where a register which is updated by a preceding instruction is used by a succeeding instruction, for example, for the generation of an operand address, is detected, the execution of a succeedingly fetched instruction is started by storing the operand address generated when the succeeding instruction is executed in association with the address of the succeeding instruction, and by using as an estimated address the operand address which corresponds to the address of the succeedingly fetched instruction and is retrieved from the stored contents.
申请公布号 US2002049895(A1) 申请公布日期 2002.04.25
申请号 US19990268998 申请日期 1999.03.16
申请人 FUJITSU LIMITIED OF KAWASAKI, JAPAN 发明人 INOUE AIICHIRO
分类号 G06F9/38;(IPC1-7):G06F9/00 主分类号 G06F9/38
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